I guess you need to be more specific:

1. nature of signal. linearity requirement on signal?
2. application of this delay? for what purpose?


naina wrote on Aug 16^th, 2017, 10:34pm:

Not sure if this meets your spec, but for analog delays an easy way is current into cap delay. The way it works is you have a fixed current that charges a capacitor. Since i = C*(dv/dt), you can solve for dt which is the delay. dv/dt = i / C; dt = dv / (i / C); where 'i' is your constant current and 'C' is the size of your capacitor. dt is the time it takes for the voltage across the cap to change exactly 'dv' volts.

Example: I usually see this implemented as an inverter driving a capacitor. The output then drives another inverter or buffer that outputs a logic signal (ENABLE, or POWER_ON_RESET, etc.). The 'dv' in this case is the switching threshold of your next stage, for example.