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Ideal SH time interleaving (Read 188 times)
John Rankin
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Ideal SH time interleaving
Aug 02nd, 2017, 5:29am
 
Hello,

I would like to use the ideal SH verilogA block to combine the outputs of a time interleaved sampler. I tried doing this by placing 2 of them in a netlist and varying the sample times, but I get an error from spectre :

FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit:
       I32:Pout_Nout_flow (from net012 to 0)

Is there a version of this model somewhere that  allows me to sample multiple nodes and combine them into one output? If not, how would you guys recommend modifying the model?

Thanks,
John
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John Rankin
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Re: Ideal SH time interleaving
Reply #1 - Aug 2nd, 2017, 5:31am
 
Just FYI here is an image of the schematic if that helps understand what I am trying to achieve.
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sh.PNG
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