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Assert statement with cadence spectre (spectre.scs) (Read 950 times)
Gp
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Re: Assert statement with cadence spectre (spectre.scs)
Reply #15 - Aug 05th, 2017, 6:38pm
 
Okay. Thanks
Now, I am clear.
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Gp
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Re: Assert statement with cadence spectre (spectre.scs)
Reply #16 - Aug 8th, 2017, 9:15pm
 
Sorry for conversation move forward. But I have a doubt.

Can we use this assertion for Verilog-AMS model? I think, this assertion only used for sub-circuit (SPICE/spectre) defination.
Any option available in spectre for Verilog-AMS assertion? pslassert option is available but I don't know how is it use.
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Andrew Beckett
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Re: Assert statement with cadence spectre (spectre.scs)
Reply #17 - Aug 9th, 2017, 11:31pm
 
Yes, provided you get the scoping correct for the assert, this will work.

Andrew.
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Re: Assert statement with cadence spectre (spectre.scs)
Reply #18 - Aug 9th, 2017, 11:34pm
 
In spectre, with assert option, I think no any option for define module name like we provide a sub-circuit name for spice schematic. So, how to pass the module name with spectre assert option?
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Andrew Beckett
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Re: Assert statement with cadence spectre (spectre.scs)
Reply #19 - Aug 10th, 2017, 11:23am
 
The sub= option (or subs=[] option) can be given the module name. Module names are essentially subckts - so doesn't need a special option.

Andrew.
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Re: Assert statement with cadence spectre (spectre.scs)
Reply #20 - Aug 10th, 2017, 10:20pm
 
Thanks. Andrew
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