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Verilog-A, one time event (Read 728 times)
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Verilog-A, one time event
Jun 05th, 2017, 12:10pm

I am developing a verilog-A model for a device. I want to write a function that is executed only one time in the simulation during the device first transition from high resistive state to a low resistive state. I looked at analog events but did not find a function that provides this functionality I want. I tried to do it using an if..else statement but it gave me convergence error.

Can someone help me with that?

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Ken Kundert
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The Spectre

Posts: 2110
Silicon Valley
Re: Verilog-A, one time event
Reply #1 - Jun 5th, 2017, 12:48pm
Try the timer event.

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