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Issue modeling sampler in RNM (Read 261 times)
Joe Shakya
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Issue modeling sampler in RNM
May 18th, 2017, 11:12pm
 
Hi,

I am trying to model an ideal sampler using RNM. But to my dismal surprise, verilog doesn't save a time point for the Real Value if the change in value is very small. This causes the sampler to miss sampling events when the next value is very close to previous value. Please see attached plot with input and output of the sampler and clock waveform. I am coherently sampling a sine wave at 1GSps and clearly the simulator is missing a time-point occasionally when vhold is very close to next sample.

This is a serious drawback for people wanting to simulate sampled data systems such as ADC using purely RNM.

Have you guys implemented a correctly behaving sampler using only RNM (no analog constructs) that overcomes this limitation?

-Joe
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« Last Edit: May 19th, 2017, 6:18pm by Joe Shakya »  

RNM_Cadence_bug_posedge_event.png
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Ken Kundert
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Re: Issue modeling sampler in RNM
Reply #1 - May 19th, 2017, 1:10am
 
Of course. Verilog-AMS is a language. You can generally write a model that behaves the way you want it to.

Perhaps you should show your model and we can see if we can determine what is going wrong.

Or, you can just use something like this ...
Code:
module adc (out, in, clk);
    output [5:0] out;
    input in, clk;
    wreal in;
    integer result;
    always @(posedge clk) begin
	  result = 64*in;
	  if (result > 63)
		result = 63;
	  else if (result < 0)
		result = 0;
    end
    assign out = result[5:0];
endmodule 



-Ken
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Joe Shakya
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Re: Issue modeling sampler in RNM
Reply #2 - May 19th, 2017, 4:43pm
 
Hi Ken,

Thanks for your response. I am modeling the ADC I am trying to build using multiple blocks since it is more complex than simple ideal adc. My problem is generating correctly sampled values as wreal, which is basic ideal sampler. The code for the sampler is pretty similar to yours and is basically following:

module sampler_ideal_w_clk ( Voutp, Voutm, Vinp, Vinm, clk );

output wreal Voutm;
input wreal Vinm;
output wreal Voutp;
input wreal Vinp;
input wire clk;

real vhold = 0.0;

always @(posedge clk)
 vhold <= Vinp-Vinm;

assign Voutp = 0.5*vhold;
assign Voutm = -0.5*vhold;

endmodule

Now my problem is that vhold doesn't have a time-point when previous value is very close to next value.

Even in you adc model, I think there will be missed digital data if the two consecutive values are very close.

-Joe

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Ken Kundert
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Re: Issue modeling sampler in RNM
Reply #3 - May 19th, 2017, 7:34pm
 
You are showing a continuous time signal. Where is that coming from? I suspect you are using Cadence's real number connect modules, which behave as you describe. In other words, the problem is not with the wreals, it is the conversion between electrical and wreal. Better if you pass the electrical signal directly into your ADC and modify the model to be like this:
Code:
module adc (out, in, clk);
    output [5:0] out;
    input in, clk;
    electrical in;
    integer result;
    always @(posedge clk) begin
	  result = 64*V(in);
	  if (result > 63)
		result = 63;
	  else if (result < 0)
		result = 0;
    end
    assign out = result[5:0];
    analog @(posedge clk);
endmodule 



-Ken
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AMS_ei
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Re: Issue modeling sampler in RNM
Reply #4 - May 19th, 2017, 11:16pm
 
Hi Ken,

In your code what is the purpose of using "analog @(posedge clk);"

Thank you.
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Joe Shakya
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Re: Issue modeling sampler in RNM
Reply #5 - May 19th, 2017, 11:26pm
 
Hi Ken,

My entire simulation is based on RNM. All my sources are also verilog-ams model generating real values based on wreals. I think the simulator is expected to process all wreals nets like a register and update value on the digital event especially when explicitly stated in the model. But it doesn't do that if the change in value is too small.

Right now I am adding kT/C noise to the input signal that seems to solve the problem. But to be precisely correct the kT/C noise should be on the sampled data not on the input signal itself. When I replace the model with real sampler, it will have twice the kT/C noise.

I liked your idea of trying to insert analog event. I tried it and I can still see missed samples occasionally.

-Joe
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Ken Kundert
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Re: Issue modeling sampler in RNM
Reply #6 - May 20th, 2017, 6:12pm
 
The '@(posedge clk);' is intended to synchronize the kernels to avoid interpolation that occurs when the the analog kernel does not place a time point at the sample time.

Your statement that Verilog-AMS ignores small changes when handling real numbers is simply not true. Something subtle is going on. If you want help on it, you need to disclose your models.

-Ken
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Joe Shakya
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Re: Issue modeling sampler in RNM
Reply #7 - May 21st, 2017, 3:57pm
 
Hi Ken,

Thanks for your reply. I have already disclosed my model for the sampler and input and output waveforms of the sampler. As you can see it is clearly not putting a time point when the next value is same as previous value. I have tightened reltol to 1e-6. But it doesn't affect at all. Also I have set maxstep to half the clk cycle. None of these seem to solve the problem.

This effect should be easily reproduced if you just create a sampler using RNM and sample input voltage at posedge clk.

I know RNM is getting processed by digital kernel hence none of the tolerance setting, which usually applies to analog kernel is making a difference. How do we specify maxstep setting for digital kernel ? And how do we specify tolerance for RNM ? Is there such simulator option ?

-Joe
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Geoffrey_Coram
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Re: Issue modeling sampler in RNM
Reply #8 - May 22nd, 2017, 8:06am
 
What Ken's concerned about is that you said your model is "basically" what you posted - but maybe not exactly, and that tiny difference that you didn't think had anything to do with the problem could be exactly what the issue is.

If you're looking for free advice Smiley, you should provide as much detail as possible so that anyone trying to help you has to do a minimal amount of work to reproduce your problem exactly.

What generates the input waveform? It has many more timepoints in the plot than the output.
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If at first you do succeed, STOP, raise your standards, and stop wasting your time.
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Ken Kundert
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Re: Issue modeling sampler in RNM
Reply #9 - May 22nd, 2017, 10:41am
 
I don't believe the problem is in the model, I believe it is in the testbench.

The best thing to do is to provide enough information so that we can replicate your simulation.

-Ken
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Ken Kundert
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Re: Issue modeling sampler in RNM
Reply #10 - May 23rd, 2017, 4:54pm
 
If your input derives from a continuous sinewave, then your problem is probably in the electrical-to-real connect module. Conversion between electrical to real in a generic connect module is very difficult to do reliably because the connect module really has very little to go on.  Cadence uses the absdelta event to update the real value when the electrical value has changed by a certain amount. It is really an unsatisfying solution, but it is hard to figure out any other way to do it if you can only observe the electrical signal. However, in your case you are building a sampler and you have both the input and clock signals. Without knowing the clock the connect module would have to generate a very rapid stream of events for the output to accurately follow the input, however with the clock you know exactly which point needs to be known accurately. You know you want accurate results at the clock edge. So you should either ...

1. convert to using a discrete sinewave generator synchronized to the clock in your testbench to generate the input stimulus, or
2. use an electrical input on your sampler and use '@(posedge clk);' to sample the input exactly at the clock edge.

You'll never solve this problem as long as there is a electrical-to-real connect module between your stimulus and your sampler, though you can reduce the problem by changing the resolution of the connect module.

-Ken
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