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Test schematic using verilogams testbench (Read 621 times)
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Test schematic using verilogams testbench
May 12th, 2017, 2:54am
I have a testbench written in verilogAMS for a CMOS integrator. Simulator ams.  As long as I run with pure verilog-A, verilogams, verliog models it works. When i try to simulate the integrator as a schematic, the simulation fails with errors of the following kind
ncvlog: *E,EXPENM (./netlist.vams,957|0): expecting the keyword 'endmodule' [12.1(IEEE)].
     module 3324d3.m.RES_POLY:schematic

It does make sense, it seems to read the resistor as a model and expects the keyword "endmodule" at the end, but since its defined as a schematic in the configuration view, it doesnt find it.

Is it possible to verify schematics using a testbench written in verilogams? In that case, any idea of any simulator setting that i might need to enable to get it working?
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Re: Test schematic using verilogams testbench
Reply #1 - May 20th, 2017, 12:02am

Create an amscf.scs file and keep it with irun command line.
Your amscf.scs file may look like this:

        portmap subckt=RES_POLY
        config cell=RES_POLY use=spice


include the library in which RES_POLY is defined.

Hope this helps.

Thank you.

Kind regards.
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