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Passive adder in continuous time delta sigma modulator (Read 896 times)
polyam
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Passive adder in continuous time delta sigma modulator
May 05th, 2017, 10:29am
 
Hi,

I am using a feedforward (FF) topology to implement my CT delta sigma modulator (CT-DSM). To implement the adder before the quantizer, I want to use a passive adder instead of an active one. In doing so, I've done a hand calculation (please see the attachment). You'll see 3 FF coefficients (k1, k2, k3) and a feedback DAC. I am using a current steering DAC.

To realize those coefficients, I am using three resistors (R1, R2, R3). A simple paper and pencil calculation was done and R1,2,3 were chosen.

I'm a little bit puzzled because when I plug in the selected R1,2,3 to the relations 1 2 3 (in the attachment) I don't get the correct coefficients. (please see (5) (6) and (7)). If I multiply (5) (6) and (7) in a constant value of 6.5 dreams come true !!!

I don't know if I've really done a right job or not !!

Any idea to resolve this problem would be appreciated.
tnx




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cheap_salary
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Re: Passive adder in continuous time delta sigma modulator
Reply #1 - May 6th, 2017, 6:32am
 
Can you surely understand |k1|+|k2|+|k3|<1.0 for passive summation ?
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polyam
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Re: Passive adder in continuous time delta sigma modulator
Reply #2 - May 6th, 2017, 8:11am
 
Hi cheap_salary,

Honestly, I guessed that but I was not sure!
So, you would say there is no way to implement a passive adder for such a noise transfer function (1-z^-1)^2? and the active one is the only solution?
What if I reduced Hinf to make the NTF appropriate for passive one?

tnx
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« Last Edit: May 6th, 2017, 7:23pm by polyam »  
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cheap_salary
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Re: Passive adder in continuous time delta sigma modulator
Reply #3 - May 6th, 2017, 9:56pm
 
polyam wrote on May 6th, 2017, 8:11am:
So, you would say there is no way to implement a passive adder for such a noise transfer function (1-z^-1)^2?
and the active one is the only solution?
No.

Surely understand passive summation.
How can you realze "K1=1.0, K2=2.5, K3=3.0" by R1, R2 and R3 ?

|K1|+|K2|+|K3|+|Kdac| > 1.0 is never possible.
Of course, you can not realize "K1=1.0, K2=2.5, K3=3.0, Kdac=-2.0".

K1=1.0, K2=2.5, K3=3.0, Kdac=-2.0
|K1|+|K2|+|K3|+|Kdac|=8.5

k1=K1/8.5=1.0/8.5
k2=K2/8.5=2.5/8.5
k3=K3/8.5=3.0/8.5
kdac=Kdac/8.5=-2.0/8.5

You have to compensate scale down of 1.0/8.5 by decreasing LSB of quantizer.
If your quantizer is a 1bit, compensation is not needed.
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polyam
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Re: Passive adder in continuous time delta sigma modulator
Reply #4 - May 10th, 2017, 9:29am
 
Thank you Cheap_salary,

It makes sense. you've made it clear to me.

One more question! Let's say the modulator is completely idealized. Should we expect a very severe performance degradation (noise shaping form, SQNR) when a passive adder is used? (comparing to let's say active adder)?

Tnx
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cheap_salary
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Re: Passive adder in continuous time delta sigma modulator
Reply #5 - May 11th, 2017, 4:46am
 
polyam wrote on May 10th, 2017, 9:29am:
Let's say the modulator is completely idealized.
Should we expect a very severe performance degradation (noise shaping form, SQNR) when a passive adder is used?
No, as far as internal ADC could be enough accurate.

In addition to accuracy of internal ADC, there is an issue of accuracy for passive summation itself.

This is true for Switched-Capacitor-DSM.
Passive summation is comprised from capacitors.
Accuracy of summation could be affected by parasitic capacitor.

Output signal of passive summation is very small, so it could be degraded by parasitic.
This is true for CT-DSM where passive summation is comprised from resistors.

However there are some merits for passive summation.
(1) No distortion
(2) High Speed
(3) Ultra low power

These are difficult to realize in active summation.
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polyam
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Re: Passive adder in continuous time delta sigma modulator
Reply #6 - May 22nd, 2017, 7:20am
 
Thank you cheap-salary. The information you gave me was helpful.
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