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Simulating the Effect of Clock Jitter on the Performance of an N-Path Filter. (Read 794 times)
Mahdi3999
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Simulating the Effect of Clock Jitter on the Performance of an N-Path Filter.
Apr 16th, 2017, 5:28am
 
Hi,

I am trying to simulate the effect of clock jitter on the performance of an N-path filter. To this end, I need to generate four 25% non-overlapping clocks. It seems that I have successfully generated these clocks; however, when using these clocks, the pss simulation does not converge!

I would really appreciate any comment!



To model the jitter, I am using the following Verilog-a code:

Code:
// VerilogA for 4thOrder, JitteryClk4, veriloga

`include "constants.vams"
`include "disciplines.vams"

module JitteryClk4(clkin, clkoutp, clkoutn, vdd, vss);

	input clkin;
	output clkoutp, clkoutn;
	inout vdd, vss;

	electrical clkin, clkoutp, clkoutn, vdd, vss;

	parameter jitter=1p;
	real statep, staten, threshold;

	analog begin

	threshold = 0.5 + ($random() % 100) * jitter/(100*50p);

	@(cross(V(clkin) - threshold))
	begin
	end
	statep = V(clkin) > threshold;
	staten = V(clkin) < threshold;

	V(clkoutp) <+ transition(statep, 0, 50p, 50p);
	V(clkoutn) <+ transition(staten, 0, 50p, 50p);
	end
endmodule 



The clkin input of the above code, which will be applied in the top-level schematic of my circuit, is a 1-GHz, 50% signal which has rise- and falltime of 50ps. (In the above code, I suppose that the jitter is 1ps and then, considering the 50-ps rise- and falltime, I calculate a threshold voltage based on the jitter and slope of the rising or falling clock. Finally, I use this threshold voltage to randomly vary the edges of the ideal input clock clkin. I hope this method is okay!).
The output of this code is a 50% 1-GHz clock where the edges experience a random jitter.

Now, I only need to generate four ideal 500MHz, 25%, non-overlapping clocks in my schematic and AND these ideal clocks with either clkoutp or clkoutn. In this way, the edges of the 25% clocks experience the jitter produced by the above code. To further clarify, I name the ideal 500MHz, 25% non-overlapping clocks Phi0, Phi1, Phi2, and Phi3. Phi0, the first 25% clock, can be ANDed with clkoutp. Phi1, the second 25% clokc, can be ANDed with clkoutn, and ...

One last point, if we assume jitter=0, the Verilog-a code will produce a delay of 25ps between the output clock (clkoutp, clkoutn) and the input clock (clkin). So I am applying an extra 25ps delay to the ideal 25% clocks. In other words, Phi0, Phi1, Phi2, and Phi3 have a delay of 25ps, 525ps, 1025ps, and 1525ps, respectively.

By the way, the AND function is achieved through the vcvsp blocks.
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Ken Kundert
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Re: Simulating the Effect of Clock Jitter on the Performance of an N-Path Filter.
Reply #1 - Apr 17th, 2017, 1:07am
 
Oh yes, this model is problematic for several reasons.  Fundamentally applying a threshold function on white noise is going to cause simulation problems, but in addition, to run PSS the system must be periodic. In otherwords, you cannot apply the jitter during the PSS analysis. The way to do this is to use the small-signal noise functions to apply the noise only during the PNoise analysis.

-Ken
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Mahdi3999
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Re: Simulating the Effect of Clock Jitter on the Performance of an N-Path Filter.
Reply #2 - Apr 17th, 2017, 2:25am
 
Thank you so much Dr. Ken.

Where should I add these "small signal noise functions"?

Although I don't know the details and algorithms of PSS, it seems quite reasonable that without a periodic response the PSS will not converge and jitter is somehow affecting the periodicity. But I'm a little bit confused! I am using the pnoise analysis to find the noise figure with the ideal clocks but the jitter can slightly change the operating point information for the PSS simulation and it seems reasonable to apply jitter during the PSS so that the operating point is calculated correctly.
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Ken Kundert
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Re: Simulating the Effect of Clock Jitter on the Performance of an N-Path Filter.
Reply #3 - Apr 17th, 2017, 12:01pm
 
The basic idea with PSS/PNoise is that the problem is split into two phases. This is generally a good idea because it can result in a much faster analysis, and because the errors created in a large signals analysis (the first phase) are confined to that phase and have little effect on the second phase (the actual noise analysis). As such, the results are generally more accurate than with a large-signal noise analysis.

In the first phase, the circuit is analyzed without considering the noise. During this phase the circuit operating point is determined. With PSS, the operating point varies with time in a periodic fashion. The circuit is then linearized about that operating point. Since the operating point is periodically varying, the linearized representation of the circuit is also time varying. This is what gives the PSS/PNoise combination its power. A linear time varying representation is able to model frequency conversion effects. Once you have a linear representation, which is created by PSS, you are ready to do a small signal analysis. It is in this phase the noise is considered.

You add small-signal noise using the noisefile or noisevec parameters of the voltage source, or with the white_noise or flicker_noise functions in VerilogA.  A Verilog-A model or a noisy square wave generator might look look something like this:

Code:
analog begin
    @(timer(0, period))
	 x = 0;
    @(timer(period/2, period))
	   x = 1;
    V(out) <+ transition( x, 0.0, period/100.0);
    V(out) <+ white_noise(pwr);
end 



For a small-signal noise analysis to work in this case, there needs to be a time where the linearized representation of the circuit is sensitive to the noise generated by the source. This will happen naturally if circuit driven by the source transitions smoothly in response the the edges generated by the source. This will certainly be true if the circuit is built from transistors. However, many people get themselves into trouble by driving a Verilog-A model with the source, where the Verilog-A model has a built in threshold. The threshold will act as a barrier to the small-signal noise, which invalidates your simulation.

-Ken
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Mahdi3999
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Re: Simulating the Effect of Clock Jitter on the Performance of an N-Path Filter.
Reply #4 - Apr 18th, 2017, 6:28am
 
Thank you so much for your priceless comments Ken.

I copied the above code, but since it had hidden states for the PSS analysis, I put ";" in front of the @(timer( , )) commands. In the transient analysis I could verify the effect of the added noise but the Pnoise results were somehow weird. Then, I checked the time domain waveforms of the PSS simulation and I observed that the clock signals remain zero all the time!

Finally, I decided to use the following code:

Code:
// VerilogA for 4thOrder, Jitter, veriloga

`include "constants.vams"
`include "disciplines.vams"

module JitterV20(clkin, clkout);

	input clkin;
	output clkout;

	electrical clkin, clkout;

	parameter pwr=16.5e-18;

	analog begin

	V(clkout) <+ white_noise(pwr) + V(clkin);

	end

endmodule
 



I put this block in the path of each of my clocks. Simulations are fast and seem quite reasonable; however, I don't know what the appropriate value of pwr parameter of the above code must be, for example, for a 5ps jitter?

Regards,
Mahdi Tavassoli
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Ken Kundert
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Re: Simulating the Effect of Clock Jitter on the Performance of an N-Path Filter.
Reply #5 - Apr 18th, 2017, 8:42am
 
You can add (* instrument_module *) to your source to suppress the hidden state check (only do this for stimulus and measurement modules).

You determine power by dividing the jitter by the slew rate as the source voltage transitions the threshold.

-Ken
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