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A simple question regarding some verilog code (Read 303 times)
wandola
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A simple question regarding some verilog code
Apr 04th, 2017, 7:25pm
 
Hi all,

I am wondering for the following code, at the rising edge of clk
what is the output when A==0.

thanks. Smiley


//------------------
always @ (posedge clk or negedge rstn)
begin
   if(rstn==0)
           out <= 0;
   else begin
           if (A==1)
                 out<=IN1;
          else
                 ;
         end
End
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Ken Kundert
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Re: A simple question regarding some verilog code
Reply #1 - Apr 4th, 2017, 11:57pm
 
if rstn is 0 output is 0, otherwise it remains unchanged.

-Ken
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wandola
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Re: A simple question regarding some verilog code
Reply #2 - Apr 5th, 2017, 6:27pm
 
got it. thanks Ken
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skyer
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Re: A simple question regarding some verilog code
Reply #3 - Apr 21st, 2017, 12:06am
 
I think it is unchanged.
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