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Common Source Amplifier with Current Mirror Load Design using gm/Id method (Read 1620 times)
Bean Nakamura
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Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Reply #15 - Apr 30th, 2017, 5:03am
 
Hello again!

I decided to continue here instead of making a new thread since what I'm about to ask is closely related to this post.

So, I have a question regarding the frequency response of CS/Diff/2-stage op amps and I hope you don't mind answering them. I have designed the amps using the gm/Id method and have met the target for the gain specs. However, I neglected to take into account the bandwidth (BW), slew rate (SR) and phase margin (PM) when designing them. Initially, I only wanted to familiarize myself with the gm/Id technique so my main focus was gain. Now I'm wondering how to design the amps taking into consideration the said specs.

Questions:-
1)How do I go about designing the amps while also taking into account the BW,SR and PM while getting the same amount of gain? Using the gm/ID method. I looked it up online and some have suggested to plot Cgs and fT when characterizing the transistor. How does this come into play?

2)I saw some formula for the transfer function of the amps posted online. In this formula, Cdb, Cgs and Cgd are also included. Would I have to plot this as well?

3)Is there an easy/intuitive way to design according to the specs for BW, SR and PM? The formula posted online looks really intimidating. I have watched several videos on the derivation and so I am familiar of the process. However, I do wish there was an easier way to do this, if possible. How is this (designing for BW, SR, PM) done in the IC design industry?

4)I will be using the designed op-amp to make a simple 3-bit ADC, is there a rule of thumb on what gain and BW I should shoot for?

Thanks in advance!
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ULPAnalog
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Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Reply #16 - May 1st, 2017, 11:30am
 
Bean

I would recommend you to have a look at the paper titled "A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on- insulator micropower OTA". This deals with the questions on SR and BW and to some extent PM while designing a two stage amplifier (although the amplifier presented in the above paper is a single dominant pole one, even without compensation). You may find it helpful.

You will notice that the dominant pole and hence the GBW of the two stage Miller compensated OTA is determined by the Miller cap and the gain of second stage and the transcondutance of the first stage among others. Also the SR is determined by the DC bias current of the first stage and Miller cap (to a large extent). I would recommend you to have a look at two stage op-amp design procedure outlined in Allen and Holberg book/lecture notes to get an idea about where to start.

If your settling error needs to be less than, say 0.1LSB (arbitrary), then your steady state error needs to be less than 0.1LSB, which sets the min DC gain. Depending on the sampling frequency and the shape of sampling clock, you would want to have a BW sufficient enough to ensure that you settle down to 0.1LSB in the track phase.
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Bean Nakamura
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Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Reply #17 - May 1st, 2017, 9:19pm
 
Thanks again ULPAnalog!
I will definitely get a hold of the materials you mentioned.
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Roy
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Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Reply #18 - May 18th, 2017, 8:09pm
 
Bean Nakamura wrote on Apr 3rd, 2017, 12:23am:
Thanks for your insights Daniel! It's always good to have someone from the industry to talk with about these kind of things. I will definitely follow in your foot steps and cover the Behzad Razavi book page by page as well as watch SCSS videos.

Thanks again!  :) Smiley





Hi, Bean Nakamura.  I'm a freshman for IC design.
If you don't mind, I want to know what is the full name of the SCSS, and where can I get their video. Thanks.

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Bean Nakamura
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Re: Common Source Amplifier with Current Mirror Load Design using gm/Id method
Reply #19 - May 18th, 2017, 10:11pm
 
Hello Roy. SSCS stands for IEEE's Solid State Circuit Society which talks about IC Design and probably some other stuff. You should be able to google their videos/tutorials online. Good luck!  :)
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