Hello all,
I have a question on designing using gm/Id. So I've successfully designed a CS Amp with resistive and PMOS active load and now I'm currently trying to design CS Amp with Current Mirror Load in 130nm using gm/Id technique. Shout out to ULPAnalog for introducing me to this technique!
Although this technique worked perfectly when designing with resistive and pmos load, the gain and output voltage was not as expected when using current mirror load. I suspect it has something to do with the output voltage or the DC operating point.


Here's what I've done:-

1)Characterized NMOS with Vdrain =0.6V, Vsource =0V , Vgate is swept from 0 to 1.2V.
The gm/Id, Id/W and gm/gds is plotted with respect to Vgs.

2)Characterized PMOS with Vdrain = 0.6V, Vsource =1.2V , Vgate is swept from 0 to 1.2V.
The gm/Id, Id/W and gm/gds is plotted with respect to Vgs.

3)Gain equation of this architecture is given by (gm of nmos)/gds,nmos+gds,pmos

4)Chose gm to be 3.14mS, assuming the desired  BW is 100MHz with load capacitance of 5pF. (I didn't simulate with the cap since my focus is the gain rather than BW don't think this matters tho).

4)DEvice dimensions
NMOS = 99um/1.5um  PMOS = 60um/1um Current = 278uA.

5)Calculated gain should be around 277V/V but the simulated gain was around 2V/V.

6)As far as the The DC operating point of the transistors, only the DC current matches the calculation. The gm of devices as well as drain voltages of the device do not match/not as expected.

7)NMOS was biased at 450mV.

9)I have attached the schematic as well as the transistor characterization plots, if it helps.

Questions:-

1)What did I do wrong or what can I change? I can't for the life of me figure it out. I did do a DC analysis using the sizing mentioned above and at the point I biased my NMOS I should have gotten close to 0.6V instead of 0.996V which is causing my PMOS to be in linear instead of saturation region.

2)Is it normal for it to have a large size? What is the typical sizing of an op amp? Does the PMOS or NMOS reach more than 100um in any case? I'm used to designing digital standard cells (which are relatively smaller) and the large size of the op amp transistor is scaring me a bit to the point where I have doubts about my design lol.

3)I suspect there is a tradeoff here between output voltage/swing and gain but I can't quite figure it out. I characterized my transistors such that the output voltage would be half of the Vdd (1.2V) for higher voltage swing. Should I re-characterize my transistors?


Any and all help is greatly appreciated and thanks in advance!
Edit: This thing won't let me attach multiple pics, will post the plots later.

Hi

I believe you are on the right track overall. The problem with active load is that you are now in a situation with two current sources connected to each other and trying to fix the operating point. Even the slightest mismatch between the currents can knock the amplifier out of its nominal operating point. This is the reason why open loop amplifiers are extremely difficult to work with.

As with most such problems, negative feedback comes to rescue. If you can set up DC negative feedback around your amplifier, you shall see it getting biased correctly as you would expect. Just to test it out, you may try adding a resistive feedback between the output of CS stage to its input and see it getting biased correctly at DC.

It's not uncommon to have 100u length transistors. In fact for me they are small!! I work with biosignal amps and flicker noise requirements at such low frequencies, in the absence of chopping forces me to use transistors whose dimensions sometimes exceed 1000u. You could literally see them.

To reiterate, I believe you are in the right track overall and enjoy designing the amps.

Best regards

On the DC negative feedback, I learnt about it during my masters, when I actually came across fully differential amplifiers. Till that point, I never really wondered on how the DC biases are set for a single ended opamp honestly. During my PhD, given that I worked in biosignal readouts, AC coupling and hence DC negative feedback became part and parcel of the instrumentation amplifiers I designed, refining my understanding of the subject. There is still a long way to go though.

Most of the things are self taught. I like to think of analog IC design as an art. Art, in general, one can teach basic principles but one can only gain mastery by practice. To me analog IC design is no different. I never really worked in "real" industry doing IC design. I work out of research labs and here there is certainly no getting started with analog IC design kind of tutorial. There are tutorials and training on how to use tools, for example cadence design suite but not on how to design circuits.

Perhaps someone from industry background can shed some light on how junior engineers are brought up to speed in IC design.

BTW, this particular reply is not design related, so I am not sure if it is appropriate to post it here.

Thanks for your insights Daniel! It's always good to have someone from the industry to talk with about these kind of things. I will definitely follow in your foot steps and cover the Behzad Razavi book page by page as well as watch SCSS videos.

Thanks again!  :)

Hello again!
Just to keep this thread going, I was just wondering if the difficulty in stabilizing the DC operating point also occurs in standard textbook differential amplifier designs with current mirror load and current mirror biasing. I haven't tried this out yet but plan to do so shortly.
You mentioned earlier that because the operating point is being fixed by two current sources, DC operating point stabilization is hard to achieve.
I would imagine this would also occur in the differential amplifier. If so, would connecting a resistor the same way as you suggested in the CS amplifier fix the problem? Or is there a more practical way of doing it that's not mentioned it literature?

A classic differential amplifier will have the problem that you encountered in CS amplifier. If you can live with lower gain, you may go for current mirror OTA with no output stage and its gain will be at best 2-5 V/V in practice.

Usually, amps are used in negative feedback systems. Unless the feedback is purely capacitive or an inductor at the input in inverting config, you will have some sort of DC negative feedback. For example as resistive gain amplifier has DC negative feedback.

Bioamps, that are capacitively coupled usually have a extremely large feedback resistance realized through pseudo resistors (very difficult to control and susceptible to PVT. Good for academic publications only). More recently switched capacitor and switched resistor feedback are getting popular for stabilizing DC operating point.

In open loop amplifier applications, the high imepdance nodes are typically charged to appropriate DC levels before the start of amplification phase. Bottom line is, if the amplifier is not properly biased at DC or before it begins to amplify the signal, it does not work as an amplifier with designed spec any more.

Thanks for your insights ULPAnalog! Definitely learned a lot here. Especially interested in those bioamps. I will definitely look into switched capacitor, switched resistor feedback circuits and the part about precharging the high impedance nodes. These are some really advanced stuff you mentioned here, it's always good to learn these kinds of things! Thanks again!

Thanks ocmb! Will get a copy of Behzad Razavi's book right away!