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Oversampling clock and data recovery for SerDes communication (Read 201 times)
bit_an
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Oversampling clock and data recovery for SerDes communication
Mar 17th, 2017, 2:29am
 
Dear Friends,
I am newbie to hardware design. I am looking forward to design an oversampling CDR. Typically it should have very fast frequency acquisition time.
In my system, I have a odd phase clock input. I am sampling my data with this clock. Now I am searching for an algorithm to detect the phase at the mid point of the data (thereby locks in no time). In theory you need a FIFO for such operation. But I am trying to avoid it as a performance measure. Typically I should need a phase selector which is driven by this algorithm.
There are papers in the web related to the topic. But being new to this field some tips and examples would be very helpful
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