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Characterization of time-based circuit PFD/TDC (Read 726 times)
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Characterization of time-based circuit PFD/TDC
Mar 14th, 2017, 6:36am

For characterizing the dynamic non-linearity of PFD or TDC(so as to calculate SNDR, HD etc), how does one generate two phase shifted signal such that the delay between them varies in a sinusoidal manner. I want to create a verilog-A model for doing this.

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Ken Kundert
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The Spectre

Posts: 2101
Silicon Valley
Re: Characterization of time-based circuit PFD/TDC
Reply #1 - Mar 14th, 2017, 9:06am
Perhaps something like this ...

module gen(out1, out2)
parameter real tclk=1u from (0:inf);
parameter real freq=1k from (0:inf);
parameter real deltat=500n from (0:tclk);
parameter real tt=10n from (0:inf);
parameter real vout=1;
real o1;

analog begin
    @(timer(0, tclk/2)) begin
	  if (o1 > vout/2)
		o1 = 0;
		o1 = vout
    V(out1) <+ transition(o1, 0, tt);
    V(out2) <+ transition(o1, tclk + deltat*sin(6.14*freq*$abstime), tt);

I have not actually tried it, but it should be close.

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