Perhaps something like this ...
Code:module gen(out1, out2)
parameter real tclk=1u from (0:inf);
parameter real freq=1k from (0:inf);
parameter real deltat=500n from (0:tclk);
parameter real tt=10n from (0:inf);
parameter real vout=1;
real o1;
analog begin
@(timer(0, tclk/2)) begin
if (o1 > vout/2)
o1 = 0;
else
o1 = vout
end
V(out1) <+ transition(o1, 0, tt);
V(out2) <+ transition(o1, tclk + deltat*sin(6.14*freq*$abstime), tt);
end
endmodule
I have not actually tried it, but it should be close.
-Ken