Hi,
I am creating a multiphase fractional PLL with Fref 6MHz and Fout 403-407MHz. Instead of generating phases from a multiphase LC-VCO, I am using RC filters to generate the phases. The phases will have errors, thus there is a phase correction circuit. This correction circuit converts the phase difference (between the phases) into voltage and compares these voltages through a error amplifier.
This phase correction unit has resistance and capacitors which are prone to errors due to mismatch and thus the generated voltages may have errors.
Through monte carlo simulation this error is visible. Without mismatch there is no phase errors, but they crop up when mismatch is taken into account.
How can I remove these errors? I have thought of dividing the erroneous divider output and reach a frequency until no errors exist. Then using a integer PLL to ramp up to 6MHz. I dont know whether this thought is vague or bad! At least I have not seen PLL within a PLL.
Please help in this regard.

At that low a frequency, why not use a ring oscillator? The phase noise (aka jitter) requirement will be the limiting issue.