The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 29th, 2024, 4:51am
Pages: 1
Send Topic Print
PLL predivision for harmonic reason (Read 1717 times)
dog1
Community Member
***
Offline



Posts: 52

PLL predivision for harmonic reason
Jan 13th, 2017, 7:23am
 
Hello everyone,

I remembered that it is beneficial to have the PLL reference clk pre-divided before feeding into the PLL to reduce the effect of harmonics, but I cannot remember how it is reasoned, nor can I reason it myself. Can anyone help me with that?

Thanks:)

CHEN
Back to top
 
 
View Profile   IP Logged
subtr
Community Member
***
Offline

Analog Enthusiast

Posts: 72
India
Re: PLL predivision for harmonic reason
Reply #1 - Jan 31st, 2017, 10:41pm
 
If you pre divide the reference clock, then it's not going to be good in terms of reference spur. The PLL bandwidth was already kept lower than undivided reference clock. Now if you lower your frequency of reference, then more harmonics of your reference feedthrough will come inside the PLL band. This is bad because now VCO is going to react to these spurs resulting in more jitter. Now what is advantage of dividing the clock? Your phase detector range increases. The same time difference between your reference and feedback clock now represents a smaller phase which means phase detector range has improved. But this comes at the cost of reduced gain.
Back to top
 
 

Regards
Subtr
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.