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Delta Sigma DAC (Read 109 times)
subtr
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Delta Sigma DAC
Jan 11th, 2017, 11:33pm
 
Hi
Say I had an 8-bit ADC which gives me all zeros to all 1's for a voltage range of 0 to 1V. This ADC feeds a delta Sigma DAC in which I will have to do some processing in digital domain. Now that I have some arithmetic to be done I'm going to come across -ve numbers that I might have to use 2's complementary. Is this a fundamental and compulsory reason why numbers have to be represented in 2's complementary fashion? I'm blinded by the fact that I still have the same 256 numbers. What do I gain by re arranging them? Embarrassed
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Andrew Beckett
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Re: Delta Sigma DAC
Reply #1 - Jan 12th, 2017, 1:04am
 
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Re: Delta Sigma DAC
Reply #2 - Jan 12th, 2017, 5:08pm
 
Hi Andrew,

Thank you for the links. But my question was not exactly what is two's complement. But as to why it helps me in underflow caused by my DSP operation. Isn't a negative number = underflow at zero? The same underflow will happen in 2's complement as well for the same operation at the most negative number.

In fact after giving a good thought, I have found that an 1 extra MSB + 2's complement is what would actually help. My 8bit data could be operated upon and result in an overflow requiring 9th bit which can be saved by using an additional bit. But bottom side for 9bit and 8bit end at zero which means underflow on the zero side cannot be take care of by the current 9bit system. But if I had a 2's complement 9bit system, it could take care of underflow. I have a picture which I used to visualize the comparisons.

Pure Binary:

0  <------------8bit--------------> Max
0  <---------------------------9bit-------------------------------> Max

Underflow not taken care in the DSP because this 9bit representation can't cannot represent -ve numbers/underflow of 8bit.

2's Complement Representation :

-Max <----------------------------9bit range------------------------------>Max
               -Max<--------------8bit range----------------->Max

Both sides overflow/underflow taken care by this 9bit system due to DSP. This is the case where overflow/underflow in 9bit does not occur. If that occurs due to addition of more than 4 8-bit numbers,a tenth bit would be required or floating point. In case you see any logical error in this I would like you to correct me because I don't have any document/link reference for this.

My conclusion from the above idea is :
1) 1 extra bit helps in overflow representation.
2) Just 2's complement without extra bit is as good as binary in terms of overflow and underflow as no range extension.
3) 2's complement with an extra bit helps both in underflow and overflow.
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« Last Edit: Jan 12th, 2017, 6:45pm by subtr »  

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