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Why should CP - PLL have limited bandwidth? (Read 420 times)
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Why should CP - PLL have limited bandwidth?
Jan 08th, 2017, 10:51pm
 
There are reasons why PLL has to have low bandwidth in comparison to Fref. I'm currently talking about a simple charge pump based PLL. One reason I know is the reference spur should be minimize because it will cause VCO to change its frequency which will again propagate through the loop. The bandwidth cannot be increased much because of the stability issue. There is a thumb rule followed by people to make the bandwidth Fref/10. My question is : Which is more fundamental reason for this thumb rule? Is it the reference spur or the stability? I realize that our s-domain wouldn't work if our bandwidth is comparable to the Fref. It's hard to decouple these because averaging and removing reference spur, by using some golden PD automatically means I'm doing a low pass in frequency domain. But it would be great if someone could explain it in simple words.
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Re: Why should CP - PLL have limited bandwidth?
Reply #1 - Mar 20th, 2017, 9:24pm
 
you don't want the loop to respond to the reference frequency on every clock edge is the primary reason. The PLL should respond to the cumulative results of multiple phase errors.
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Re: Why should CP - PLL have limited bandwidth?
Reply #2 - May 30th, 2017, 1:32pm
 
Depending on what specs you are trying to meet the loop bandwidth is either set to insure stability, minimize reference spurs, minimize integrated phase noise, or minimize contribution of Delta-Sigma Modulation noise.

In my experience, mostly working on PLL's in communication systems, the loop bandwidth is usually set to optimize integrated phase noise.   This bandwidth usually tends to be close the offset frequency for which the contribution from the PLL noise sources (ref, PFD, CP, divider, loop filter) which tend to be flat wrt offset frequency is equal to the VCO noise contribution (which tends to be dropping 20dB/dec wrt offset frequency).
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Re: Why should CP - PLL have limited bandwidth?
Reply #3 - May 30th, 2017, 1:38pm
 
The fundamental reason for the 1/10 rule is the phase shift from the so-called "divider delay" (which is probably more accurately labeled "sampling delay").     Because the PFD only samples once every reference clock there is an equivalent average delay of 0.5/fref so in S-domain terms this can be expressed as exp (-0.5 * S / fref ).    The phase shift of this sampling delay at fref / 10 is about 18 degrees.      Any more phase shift than that and it gets pretty hard to stabilize the loop.
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