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Why should CP - PLL have limited bandwidth? (Read 253 times)
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Why should CP - PLL have limited bandwidth?
Jan 08th, 2017, 10:51pm
 
There are reasons why PLL has to have low bandwidth in comparison to Fref. I'm currently talking about a simple charge pump based PLL. One reason I know is the reference spur should be minimize because it will cause VCO to change its frequency which will again propagate through the loop. The bandwidth cannot be increased much because of the stability issue. There is a thumb rule followed by people to make the bandwidth Fref/10. My question is : Which is more fundamental reason for this thumb rule? Is it the reference spur or the stability? I realize that our s-domain wouldn't work if our bandwidth is comparable to the Fref. It's hard to decouple these because averaging and removing reference spur, by using some golden PD automatically means I'm doing a low pass in frequency domain. But it would be great if someone could explain it in simple words.
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Re: Why should CP - PLL have limited bandwidth?
Reply #1 - Mar 20th, 2017, 9:24pm
 
you don't want the loop to respond to the reference frequency on every clock edge is the primary reason. The PLL should respond to the cumulative results of multiple phase errors.
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