Andrew Beckett
Senior Fellow
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Life, don't talk to me about Life...
Posts: 1742
Bracknell, UK
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You didn't really show what you have in the circuit to which the output of this Verilog is connected, but assuming it's just to an ideal capacitor, then what you're probably seeing is the RC caused by the output impedance of the L2E connectmodule (or whichever connect module you're using).
Most of the built-in connect modules have a default output impedance of 200 ohms, which would give a time constant of about 0.2ns with a 1pF cap - so that looks roughly right from the curves you've plotted.
You can reduce that - mostly you want a non-ideal connect module to better represent how the actual driver would behave when connecting to an analog circuit - in real life it wouldn't have zero output impedance.
Regards,
Andrew.
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