The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Apr 16th, 2024, 10:49am
Pages: 1
Send Topic Print
sub-threshold design of MOSFET for 45nm technology (Read 1965 times)
joy
New Member
*
Offline



Posts: 2
Bengaluru
sub-threshold design of MOSFET for 45nm technology
Dec 17th, 2016, 9:46pm
 
Hi all,

I want to design a op-amp for 45nm technology which is operating in sub-threshold region
can any one give me the ID and gm equations which can be used for hand calculations in BSIM3 model, i am using a cadence virtuoso simulator .

Thank you
Back to top
 
 
View Profile   IP Logged
lpalocko
New Member
*
Offline



Posts: 2

Re: sub-threshold design of MOSFET for 45nm technology
Reply #1 - Jan 27th, 2017, 3:56am
 
Hi,

why do you want to use exactly the BSIM3 model?

LP
Back to top
 
 
View Profile   IP Logged
Andrew Beckett
Senior Fellow
******
Offline

Life, don't talk to
me about Life...

Posts: 1742
Bracknell, UK
Re: sub-threshold design of MOSFET for 45nm technology
Reply #2 - Jan 29th, 2017, 1:01am
 
The model equations are documented in the MMSIM documentation - if you invoke <MMSIMinstDir>/bin/cdnshelp you'll find it under the "MMSIM" section in the documentation (I can't remember the manual name off the top of my head, but it's got something like Model Equation Reference in the title). There's a chapter on bsim3v3 and another on bsim4. Most likely any 45nm PDK (such as the Cadence Generic 45nm PDK, gpdk045) will use bsim4, not bsim3v3.

Regards,

Andrew
Back to top
 
 
View Profile WWW   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.