Dear All,

From the measurement results (attached Fig) of a JSSC paper "A CMOS 110-dB@40-kS/s Programmable-Gain Chopper-Stabilized Third-Order 2-1 Cascade Sigma-Delta Modulator for Low-Power High-Linearity Automotive Sensor ASICs", it seems that choppping at lower frequency (Fs/2), some kind of noise folding happens. I built a similar design (2nd FF SC SDM with chopping used in the 1st stage) and saw similar results in my transistor-level simulation (no mismatch is added into simulation!). In many papers, people just choose Fs/2 as chopping frequency but never explain why. Could someone provide some insight on this issue?

Thanks!

Hi deba,

This is true for a continuous time SDM, however, for a switch cap design, if you chop at proper time (eg. middle of sampling phase), I didn't see any direct correlation between chopping action and feedback signal. If you look at this paper"On Chopper Effects in Discrete-Time ΣΔ Modulators", the author concluded that noise folding happens due to unmatched parasitic caps around OTA, but in my simulation, there is no mismatch but I still see noise folding...

Thanks,
Long