Lala878
Junior Member
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Posts: 18
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Hi all,
I've been making verilog-ams models and simulated them using AMS Designer in Virtuoso. So I've been making my testbenches in schematics and ran the simulations with ADE. I've been using test generators from analogLib and whenever I had design variables I would use them in my models with out-of-module-referencing (ex. cds_globals.var ). But lately, I need to change my testbench designs...I have to make my own voltage source module and now I need to have a way set global variables and if in a testbench I'm using more voltage sources, I need to pass them different values of the global variables...
like I saw being used in "textual top-level testbenches" as: vsource #(.dc(1.8), .type("dc")) V1 (vdda, gnda);
I tried making my own mycds_globals.vams file but the ncvlog would report an error saying I'm duplicating/redefining worklib.cds_globals
My question is is there a way to make have global variables file using ADE with AMS Designer? And, where exactly should I include a path to my_disciplines.vams so as to when I include them in my module I can just write `include "my_disciplines.vams" instead of `include "/full/path/to/my_dicsiplines.vams" ?
Thanks in advance
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