Geoffrey_Coram
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I've seen schematic interfaces that allow "iterated components" where you can use vector notation for them (and the nodes connected to their terminals). But I think these are expanded into a "systematical naming scheme" that you mention.
You might be able to do something with the generate statement in Verilog-AMS, if your simulator supports that.
Otherwise, I think you'll have to write a script that generates your netlist, and then you might as well come up with a naming scheme, in case your Spice simulator doesn't like vectors.
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