Hello everyone:
I found there is not a lot concrete materials on reset timing on the Incremental ADC. Right now I am doing a MASH 2+2 structure incremental ADC. assume there will be a ideal digital error cancellation logic (digital differentiator ) on 2nd stage path as (1-z^-1)^2. May I ask how large the delay is introduced in this differentiator? Intuitively I thought it is two regardless reset cycles? Please let me know your ideas.
since in incremental adc application, we will reset every OSR cycles, these block introduce large delay is not good.