The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 28th, 2024, 9:13am
Pages: 1
Send Topic Print
Design of CMOS PLL with Ring VCO (Read 1612 times)
Bomestantin
New Member
*
Offline



Posts: 1

Design of CMOS PLL with Ring VCO
Aug 29th, 2016, 10:00pm
 
I need to design PLL that works in wide frequency range and have a small power consumption. So i desided to use Ring VCO in this PLL. Also i am using TSPC frequency divider, because PLL should have pretty high max frequency. The problem is, that Ring VCO has a wider working frequency range than divider. If in locking process voltage on tune input of VCO will be too small or high - PLL fails to lock. I am working on pretty lame process so due to PVT i have to do VCO with wide frequency range, and also due to PVT i can't do wider range of divider. What can i do with this?
Back to top
 
 
View Profile   IP Logged
vroy_92
Junior Member
**
Offline



Posts: 30
Leuven, Belgium
Re: Design of CMOS PLL with Ring VCO
Reply #1 - Sep 2nd, 2016, 8:54am
 
Split the locking process into two parts:
During the first part, do not close the PLL loop through the feedback divider but do some sort of calibration to bring the frequency close enough to whatever frequency you want the PLL to lock at.
And then the close the loop so that the phase will be locked.

Alternatively, you can put a divide by 2 at the front of the feedback divider but then you would be limited solely to even division ratios.

I strongly recommend doing a frequency calibration first.

Back to top
 
 

Regards,
V Roy
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.