Lala878
Junior Member
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Posts: 18
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Hi all,
I am having trouble writing a model in Verilog-AMS using wreal types. It's a model of a PLL and I was given a huge testbench that was made for the transistor level design, etc. ...
anyway, I am still a newbie and for starters I just want to check the values of the ports I am trying to use...
The PLL uses fractional N divider block and I wanted to make use of the signals to build the output of the feedback loop...
The equation for output frequency consists of 30-bit input signals and 7-bit input signals. I am having trouble defining them and driving them in my testbench to test if the values are handled correctly in the buses.
This is what I did (conceptually):
module fracN_div(in, out, dig1, dig2) input wreal in; real rin; input dig1, dig2; wire [7:0] dig1; wire [29:0] dig2;
... ... endmodule
making a schematic testbench in AMS Designer (virtuoso), how can I define the bits of the dig1 and dig2 to be made of digital signals? I tried hooking them up to a vdc of 1.1V input (the specified input of signals) for logic 1 and hooked them to gnd for logic 0, but when I check the wire values using $display I get weird outputs (00000x0 or 0) (I have connected them so that it should read 7'b2 ) I tried stating them as logic but that is by default in verilog-ams and it didn't help...
can someone help?
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