No you cannot. You cannot assign both the voltage and the current of a branch. In Verilog-A branches are either voltage or current sources, and you specify the voltage or current of the source. In your model you are trying to make the same branch both a voltage and a current source. That is impossible.
Instead, model a short (0-volt voltage source) between the two nodes, like this ...
Code:module current_probe(p, n);
electrical p, n;
branch (p, n) short;
analog V(short) <+ 0;
endmodule
Or like this ...
Code:module current_probe(p, n);
electrical p, n;
analog V(p,n) <+ 0;
endmodule
You seem to have the wrong mental model for Verilog-A. To understand it better, you might want to take a look at this
Verilog-A tutorial.
Thanks for providing a simple model and providing the whole model. It makes it much easier to understand what is going on.
-Ken