seekconfessor
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hello, all: I am designing a fractional N synthesizer in GFSK modulation. I am wondering how to make sure that the control voltage Vc of VCO is set to reasonable value when PLL is locked? i.e. the dynamic range of Vc is 0.3V~0.9V, if Vc is 0.3V when PLL is locked, the linearity and dynamic range is highly limited when used for GFSK modulation. Thanks.
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