Well, in your testbench you did not actually pass anything into your current checker:
Code:curr_bfm Icurr_bfm (
.check_curr1() <---- this cannot be right
);
Second, you should never use $cds_iprobe unless you know what you are doing. It is inaccurate and when used in a circuit like this causes instabilities. Specifically, if you use $cds_iprobe you must first understand that it is inaccurate and how it is inaccurate so you know whether you can tolerate that inaccuracy. Second, you should never use the output of $cds_iprobe to drive the circuit itself.
Code:module curr_bfm(check_curr1);
output check_curr1;
electrical check_curr1;
real real_cur;
analog begin
real_cur = $cds_iprobe("tb_top.test.out");
I(check_curr1) <+ real_cur;
end
endmodule
Instead, you should just use the normal mechanism for measuring current in Verilog-A.
Code:module curr_bfm(check_curr1);
electrical check_curr1;
real real_cur;
analog begin
real_cur = I(check_curr1);
end
endmodule
Finally, this collection of models seems overly complicated and hopelessly confused. Perhaps if you described what you wanted to do we could just tell you how to do it. Regardless, you should read
Introduction to Verilog-A.
-Ken