The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 28th, 2024, 3:55pm
Pages: 1
Send Topic Print
Simulation of Digital class D amplifier using Cadence AMS simulation (Read 1538 times)
ananya
New Member
*
Offline



Posts: 3

Simulation of Digital class D amplifier using Cadence AMS simulation
May 02nd, 2016, 11:31am
 
Hello!

I am simulating a closed loop digital class D amplifier system using ams.
The system consists of behavioural Verilog models for the digital portion (digital filters and pulse width modulator) of the system. The analog portion (the ADC and the antialias filter) is modelled using ideal components from analogLib.

I have the same system in Simulink which works as expected. However, the ams simulation doesn't seem to give the same result as Simulink. In fact, i know that the result is not what I expect.

I found out that if I make the first integrator of the delta sigma ADC using ideal VCVS with lower voltage limit, the system works. But that's not a practical case and my actual ADC (with transistor level modelling) has much higher output swing limits.

Any suggestions on how to debug would be really helpful.

Thanks & regards,
Ananya
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.