In my model, charge of a nonlinear capacitor is given as Q=f(V2,V3)*Vc where V2, V3 are terminal or bias voltages and Vc is the voltage across capacitor. Current through capacitor can be given as I=ddt(Q). Can I also write I=ddx(Q,V2)*ddt(V2)+ddx(Q,V3)*ddt(V3)+f(V2,V3)*ddt(Vc)?
Whenever I am replacing 1st expression by the second expression, my AC results matches but transient result do not match. Is it wrong to use ddx or is there any restriction in verilog-a for using ddx?

Thank you Ken,

I might have written Q=c*V here, but in verilog I am not writing it as I=c*ddt(V). I always use I=ddt(Q). So in reality there is nothing like C in my equation. I just use the word capacitor for easy communication.