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Stopping HSPICE from within Verilog-A (Read 1654 times)
AA
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Stopping HSPICE from within Verilog-A
Apr 25th, 2016, 1:43pm
 
Hello everyone!

Is there a way to dynamically stop HSPICE simulation (including sweeping) from within a verilog-a module?

For example, we perform a very long transient analysis like this:

Code:
.tran 0.1n 50u sweep monte=50 



And in our verilog-a module, if a condition is satisfied, we need to stop the simulation (including sweeping). For example:

Code:
if (state==done_state) begin
  // I would like to stop hspice here
  // there must be a command in verilog-a that is
  // similar to $finish() in digital verilog
  // Anyone please?
end 



My HSPICE version is 2013.03-SP2.

Thank you.
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Geoffrey_Coram
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Re: Stopping HSPICE from within Verilog-A
Reply #1 - Apr 26th, 2016, 6:41am
 
The Verilog-A language provides $finish and $stop; you can try those and see if they work for what you want to do.
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If at first you do succeed, STOP, raise your standards, and stop wasting your time.
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