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global parameters in Verilog-A? (Read 1695 times)

danmc Community Member Offline Posts: 35 Boston	global parameters in Verilog-A? Apr 12^th, 2016, 9:23am Is there a way for a Verilog-A and/or Verilog-AMS module to be able to access a global design parameter? Is the only way to pass it as an instance parameter to the module? Thanks -Dan
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cheap_salary Senior Member Offline Posts: 162	Re: global parameters in Verilog-A? Reply #1 - Apr 12^th, 2016, 7:34pm Use Macros. Macro's value can be passed by simulator command option. For example, spectre -va,define MACRO=value
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