Sx_cut wrote on Apr 10th, 2016, 8:26am:Dear all,
In order to acquire linearity and SNR plots for the ADC we typically require hundreds of thousands of sample points (depending on resolution of ADC). Usually people have large on chip memories to deal with such massive amount of data. They dump the data in memory and perform read out at a slow rate (Memory write is still limited to around less than 1GHz so high speed ADCs are usually interleaved).
The problem is I don't have the luxury of having a memory at the moment and I have to rely on high speed IO for that matter. I am new to high speed IOs, so can you tell me what IO architectures can I use with my ADC with data output rate of 1Gbps? FPGA will serve as data acquisition instrument.
Simply put, any thoughts of how to handle massive 32 bit data coming out of ADC at 2Gbps?
You could sub-sample the output (i.e. output every other data point). The result will be an aliased version of the ADC output but you can account for that mathematically. I guess this is commonly done for papers. You could also use twice the number of outputs working at 1/2 the rate.
I'm not sure why you are outputting 32 bits.