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Environment Vars for VCS tool (Read 2285 times)
AA
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Environment Vars for VCS tool
Mar 30th, 2016, 6:55am
 
Hello!

Apologies if my question is trivial, but please, I'm new to verilog-a.

Currently, I'm using hspice as my verilog-a simulator, i.e., to test a verilog-a module, I'll have to
create an hspice netlist (as my test bench), and "hspice" the netlist. Works, but I wish to write
my test bench in verilog-a too. I guess it's easier to control a verilog-a test bench than an hspice one (IMHO at least).

I heard about the Synopsys VCS tool, in which you can write your test bench in verilog-a too.
I tried to start this tool by the command "vcs", but I got the error "command not found".

I guess the tool is installed in my school's linux system, but I probably need to set some environment vars to get it to work.
Also, I know the Synopsys installation path, but I could not locate where is the VCS tool inside that path.

Can anyone tell me how to setup/start the VCS tool please?

Thank you!
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Geoffrey_Coram
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Re: Environment Vars for VCS tool
Reply #1 - Apr 11th, 2016, 9:23am
 
I think VCS (and other tools that take "Verilog") as an input will simulate digital Verilog (IEEE Std 1364) and/or SystemVerilog (IEEE Std 1800).

I am not aware of a simulator that takes Verilog-A as an input netlist, and Verilog-A doesn't have a way to represent the .tran/.dc/.ac analysis cards for simulation.
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