Hi,

In the schematic we can define pins like lets say out<0:16> and create a symbol with just one pin and then in the top level schematic we can label pin like out<0> out<1> out<2> and so on so forth.
How can I do something similar in my Verilog-a module?
I have defined output voltage like this:

out[i]=Ac*sin(phase+i*2.0*`PI/N);

Now if I have a bunch of phases and I don't know how to deal with this problem.  :'(
What I can do is really in an amateur way like defining
out[1]=Ac*sin(phase+1*2.0*`PI/N);
out[2]=Ac*sin(phase+2*2.0*`PI/N);
.
.
.
and creating a bunch of pins for the symbol.

Thanks for any help.