I am designing synchronous buck converter with following specifications
fs=1MHz, L=1uH, C=200uF, Vin=5V, Vout=1.8V, R=3ohms, PWM Ramp VM=1V.
I am trying to do PSS/PAC analysis in cadence to find uncompensated open loop gain. I am assuming control voltage vc=0.36V which is applied to a comparator +ve terminal. -ve side of comaparator is connected with sawtooth(tr=999n,period=1000n)
This is transient output of vout(voltage across capacitor)
This is our PAC output