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Jacki

Senior Member

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Posts: 237

Two VerilogA files output data with different frequency. Why?
Jan 27^th, 2016, 7:52am

Hi,
I have two VerilogA files, the functions are same. But one output the data in a double frequency of the other one. Can anybody tell me why?

File 1: output the data V(out) in normal clock frequency

for (i=0; i<1024 && !$feof(pwmfileA); i=i+1) begin
$fscanf(pwmfileA,"%b\n",pwm_A[i]);
$display(pwm_A[i]);
end

$fclose(pwmfileA);
@(cross(V(clk) - thresh, +1)) begin
if(k<1024) begin
hold = pwm_A[k];
k=k+1;
end else hold=0;
end
V(out) <+ 1.2*transition(hold, dy, tr, tf);

File 2: output the data V(out) in twice frequency

@(cross(V(clk) - thresh, +1)) begin

if(k<1024 && !$feof(pwmfileA) ) begin
$fscanf(pwmfileA,"%b\n",hold);
k=k+1;
end else hold = 0;

end // cross

V(out) <+ 1.2*transition(hold, dy, tr, tf);

Thank you.

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Geoffrey_Coram

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Posts: 1998
Massachusetts, USA

Re: Two VerilogA files output data with different frequency. Why?
Reply #1 - Jan 28^th, 2016, 6:13am

The difference in your models appears to be that one reads the data outside the cross event, and the other reads it inside. �Does the first model read the data on every timepoint? �I don't see what would keep it from doing so, but you have left out much of the model code (eg, the $fopen call and initialization of k).

Are you sure the clocks are the same? �Are you sure your cross event has +1 for the direction argument for both models?

You could put in a $strobe to report the time for each crossing and see if the second model reports additional crossings.

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Jacki

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Posts: 237

Re: Two VerilogA files output data with different frequency. Why?
Reply #2 - Feb 1^st, 2016, 3:07am

Geoffrey_Coram wrote on Jan 28^th, 2016, 6:13am:

The difference in your models appears to be that one reads the data outside the cross event, and the other reads it inside. �Does the first model read the data on every timepoint? �I don't see what would keep it from doing so, but you have left out much of the model code (eg, the $fopen call and initialization of k).

Are you sure the clocks are the same? �Are you sure your cross event has +1 for the direction argument for both models?

You could put in a $strobe to report the time for each crossing and see if the second model reports additional crossings.

Hello Geoffrey,

Thank you for your comments. The problem is solved, and the problem is the file was read every other line, and the frequency is double.
By the way, could you please suggest how to define a variable parameter in Verilog A?
Currently, I define a variable parameter in Verilog A, and after I create the symbol, I try to change the value of the defined parameter in the symbol, it seems the value is not changed at all. I have to edit the Verilog A script every time to change its value. It is a bit boring and not convenient for a large number sweep.

The variable parameter is defined as below,

parameter tr=1n, tf=1n, dy=0;

After creating the symbol, I do see them in the "CDF Parameter of View" in the schematic view. Shall I add more command to complete the definition?
Thank you.

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Jacki

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Posts: 237

Re: Two VerilogA files output data with different frequency. Why?
Reply #3 - Feb 1^st, 2016, 11:43pm

Jacki wrote on Feb 1^st, 2016, 3:07am:

Geoffrey_Coram wrote on Jan 28^th, 2016, 6:13am:

The difference in your models appears to be that one reads the data outside the cross event, and the other reads it inside. �Does the first model read the data on every timepoint? �I don't see what would keep it from doing so, but you have left out much of the model code (eg, the $fopen call and initialization of k).

Are you sure the clocks are the same? �Are you sure your cross event has +1 for the direction argument for both models?

You could put in a $strobe to report the time for each crossing and see if the second model reports additional crossings.

Hello Geoffrey,

� �Thank you for your comments. The problem is solved, and the problem is the file was read every other line, and the frequency is double.
� �By the way, could you please suggest how to define a variable parameter in Verilog A?
� �Currently, I define a variable parameter in Verilog A, and after I create the symbol, I try to change the value of the defined parameter in the symbol, it seems the value is not changed at all. I have to edit the Verilog A script every time to change its value. It is a bit boring and not convenient for a large number sweep.

� �The variable parameter is defined as below,

parameter tr=1n, tf=1n, dy=0;

� �After creating the symbol, I do see them in the "CDF Parameter of View" in the schematic view. Shall I add more command to complete the definition?
� �Thank you.

I find the problem is I miss the type definition of the parameter. I redefine the parameter as
parameter real tr=1n, tf=1n, dy=0;

But for a single simulation, it Works well, when I start the parameter sweep in ADE XL, the results are quite bad. I couldn't figure out why.

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