Hi guys,

So i'm quiet new to the verilog ams but it has been over 2 weeks that i'm working on it. I read all the posts before coming here, several docs on cadence and some literature.
Anyway i have a problem with the connection between an analog module (resistance) and a digital one (clock generator). Both these modules were taken on this page's tutorial on verilogAMS.

ncelab: *E,CUVNCM (./test_res.vams,12|35): No connection module found:Need an input port of discrete discipline logic, and an output port of continuous discipline electrical, at instance top.clock_gen1.

i already checked the libraries and i do have the connetLib. The automatic insertion isn't working based on the error.

Please help i have no more ideas

Thank you for your replies

what is the code in line no. 12 of that file?