The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Apr 25th, 2024, 3:52am
Pages: 1
Send Topic Print
How to read a *.log file into VerilogA? (Read 4464 times)
Jacki
Senior Member
****
Offline



Posts: 237

How to read a *.log file into VerilogA?
Jan 14th, 2016, 10:08am
 
Hello,

   I am quite new to VerilogA. Currently I want to read a .log file into VerilogA and use the transition filter. The file is just a lot of "0" and "1", and either "0" or "1" in each line. How can I read it correctly? I try to use fscanf(), but I get the syntax error. Could anybody help me to correct the error?

// VerilogA for VerilogA, readfile, veriloga

`include "constants.vams"
`include "disciplines.vams"

module readfile (clk, out);
 input  clk;
 output out;
 electrical out, clk;

 integer pwmfileA;
 real hold;
 real pwm_A[0:1024];
 genvar i, k=0;
 parameter real thresh=0.6;
 parameter tr=1n, tf=1n, dy=0;
 integer j=1;
 
analog begin

 @(initial_step) begin
   pwmfileA = $fopen("./pwm_A.log","r");  // here report an error
   $fclose(pwmfileA);
   end

   for (i=0; i<1024; i=i+1) begin    
     pwm_A[i] = $fscanf(pwmfileA,"%d",j);  //here report an error
     j=j+1;
   end
                 
 for (k=0;k<1024;k=k+1) begin
   @cross(V(clk)-thresh, +1)
     hold = pwmfileA[k];
     V(out) <+ 1.2*transition(hold, dy, tr, tf);
 end
end
endmodule

the reported errors are shown here:
Error found by spectre during AHDL compile.
   ERROR (VACOMP-1149):
       "./veriloga.va",
       line 26: Genvar loop evaluation failed. Check whether `/usr/bin/perl'
       is available.
   ERROR (VACOMP-1816): Exiting AHDL compilation.

   Any comments are welcome.
   Thank you.
   Jacki
Back to top
 
 
View Profile   IP Logged
Jacki
Senior Member
****
Offline



Posts: 237

Re: How to read a *.log file into VerilogA?
Reply #1 - Jan 15th, 2016, 12:17am
 
Hi,

   In fact, my question can be simplified to be "how to read a text file into a vector"? The text file has 1024 lines, each line is a binary data either "0" or "1".

   Thank you.
   Jacki
Back to top
 
 
View Profile   IP Logged
Jacki
Senior Member
****
Offline



Posts: 237

Re: How to read a *.log file into VerilogA?
Reply #2 - Jan 15th, 2016, 3:51am
 
Problem has been solved.

Thank you.
Back to top
 
 
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1998
Massachusetts, USA
Re: How to read a *.log file into VerilogA?
Reply #3 - Jan 18th, 2016, 8:08am
 
For others reading this post, you might want to mention how you fixed it.

For my part, I suspect the problem is that you $fclosed the file in @initial_step, so that it was not open when you tried to $fscanf.
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
Jacki
Senior Member
****
Offline



Posts: 237

Re: How to read a *.log file into VerilogA?
Reply #4 - Jan 25th, 2016, 4:30am
 
Geoffrey_Coram wrote on Jan 18th, 2016, 8:08am:
For others reading this post, you might want to mention how you fixed it.

For my part, I suspect the problem is that you $fclosed the file in @initial_step, so that it was not open when you tried to $fscanf.


Hello Geoffrey,
   Thank you very much for your reply. The problem has been solved. The reason for the slow simulation is I define a very big array, and use this array to read in the data file. This array occupies a lot of memory. If I remove this array. The speed is fine.
   By the way, do you know how to read a read starting from the middle part?
   Currently I only know to read in a file starting from the beginning.
   For example:
fileA = $fopen("./A.log","r");
$fscanf(fileA,"%b\n",hold);
   If I want to read in the data from some middle part in the file A.log, can you please suggest how I should do it?
   Thank you.
Back to top
 
 
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1998
Massachusetts, USA
Re: How to read a *.log file into VerilogA?
Reply #5 - Jan 25th, 2016, 7:13am
 
VAMS LRM 2.4 section 9.2 / table 9-2 says that $fseek is supported in the analog context, so I suppose it's just a question of whether your simulator supports it.
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
Jacki
Senior Member
****
Offline



Posts: 237

Re: How to read a *.log file into VerilogA?
Reply #6 - Jan 25th, 2016, 11:35pm
 
Geoffrey_Coram wrote on Jan 25th, 2016, 7:13am:
VAMS LRM 2.4 section 9.2 / table 9-2 says that $fseek is supported in the analog context, so I suppose it's just a question of whether your simulator supports it.


Hi Geoffrey,

   Thank you very much. I will try it.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.