Hi all,

I am trying to hierarchically probe a current at the port TEST of instance DUT in a mixed-mode simulation using the $cds_iprobe command in a Verilog-AMS module. However, it doesn't work and during simulation I get the following warning at time 1.999ms (that is the time when I execute the $cds_iprobe command):

"Warning from spectre at time = 1.999 ms during transient analysis `tran'. WARNING: Can not create '-flow' probe on DUT.TEST, it might be an internal node or not present in the design."

I have set up the simulation as follows:

I use an Ocean script to start the simulation (ams simulator, Spectre solver, AMS Unified Netlister with irun). In that Ocean script I save the current:

saveOption( 'currents "selected" )
save( 'i "/DUT/TEST" )

This creates a probe in the probe.tcl file in the netlist folder, such as demanded in the Cadence Verilog-AMS Language Reference ("You must have an active Tcl current probe set up to probe the current that the $cds_iprobe task returns."):
probe -create -emptyok -database ams_database -flow {sim_regression_1.DUT.TEST}

The current probing itself works, as after the simulation I can display the current waveform in Viva. Therefore I do not understand why the $cds_iprobe command leads to the above mentioned warning message.

It would be great if someone could help me with this issue.

Kind regards, Gerhard

Hi Geoffrey,

Thanks for you response. I have found the cause for the issue.

The current probe is present at startup. I have defined that probe in the Ocean file and then it has been automatically added to the probe.tcl file. The probed port is listed there as "sim_regression_1.DUT.TEST". However, I have probed the node "DUT.TEST" with the $cds_iprobe command, which caused the probing to fail.

Using the port name as stated in the probe.tcl file now shows effect, but not the desired one. The simulator does not any more issue a warning message, but hangs when it should execute the $cds_iprobe command.

I have decided to implement a workaround. The port of interest is part of a Verilog-AMS module, so inside that module I created an internal node and assigned the current through the port to that node.

V(internal_node) <+ I(TEST);

Now I probe the voltage of that internal node instead of the current though the port, which works without problems.