I am trying to write some code for a digital circuit.

module Processor(count,residue,out)
input [7:0] count;
input [4:0] residue;
output [12:0] out;

wire [12:0] mem, tmp1,tmp2,tmp3;

reg [4:0] coeff = 5'b10110;

assign tmp1 = count*coeff;
assign tmp2 = tmp1 + residue;
if (tmp1>mem)
  assign tmp3 = tmp2-mem;
else
 assign tmp3 = tmp+coef - mem;

assign mem = tmp2;
assign out = tmp3;

endmodule

I am using cadence nc-verilog for the design. the error msg says
if(tmp3 > mem): illegal operand for constant expression

can anybody help with this? really confused... Or, how shall I manage this?