Your intuition seems way out of whack when it comes to Verilog-A. The contribution statement is really an equation (with the constraint that the left-hand side must be a signal) rather than an assignment.
In an assignment it makes perfect sense to say:
Code:i = i;
In doing so, you don't actually change
i. But as an equation it makes no sense. It contains no information. If you try to use:
Code:V(vA) <+ V(vA);
in the simulator you will end up with a singular Jacobian. Essentually you have more unknowns than you have equations because one of the equations you gave was defective.
Perhaps if you took a look at
Introduction to Verilog-A it would help.
Of course there is another issue with what you propose. You are driving V(vA) with a voltage source, meaning that its voltage could not be affected by the outside circuit. Perhaps what you want is to add a switch. Something like
Code:if (trg > 0.75)
V(vA) <+ reset;
else
I(vA) <+ 0;
. But doing so seems like a very bad idea, as you are driving your input. You are very likely to build either an oscillator or an unresetable latch.
-Ken