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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › Veriog ams for voltage controlled oscillator: output frequency= input*gain
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Veriog ams for voltage controlled oscillator: output frequency= input*gain (Read 1108 times)
Rosh
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Veriog ams for voltage controlled oscillator: output frequency= input*gain
Oct 13th, 2015, 8:13pm  
Hi

I want to build a verilog ams based clock pulse generator which takes in an input voltage and then gives me a frequency which is a particular gain*input voltage

How do I implement this particular frequency voltage relation?
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