I am designing ampilfier circuit in cadence virtuoso using gpdk45nm technology spectre model file. I am finding difficulty in figuring out the exact mobility of either of pMOS or nMOS transistors. For example, in one of the geometrical model in file the mobility of pMOS is given as u0=0.02305+du0_p and for nMOS u0=0.01528+du0_n. In typical-typical standard process (given in file) the value for du0_p and du0_p is 0, which means that mobility of pMOS is greater than nMOS which is not possible. All the initial values of pMOS is greater than nMOS in all the geometrical models given in file. Mobility of holes can never be greater than electrons. So, how these mobility values are decided or there is another method to estimate the mobility values of nMOS and pMOS. Please reply soon.

There are cases when the mobility of holes can actually be found greater than electrons. Especially in strained silicon cases and when SiGe are used, this could lead to higher hole mobility.
Also based on the orientation of the Cristal and carrier flow the mobility can change.

http://www.sciencedirect.com/science/article/pii/S0961129006715903

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