The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Mar 28th, 2024, 1:49pm
Pages: 1
Send Topic Print
Functions outside module with internal variables (Read 10097 times)
PN03
New Member
*
Offline



Posts: 8
France
Functions outside module with internal variables
Jul 30th, 2015, 7:29am
 
Hello,

I'm a new user of Verilog-A/SPICE for 2 months. I'm trying to model some specific basic components (R, L, C and G) with complex functions. I mean for example that the capacitance C is a function of several parameters including conditional tests (if, else) and loops (while).

To do that, I would like to write a set of functions that I can use and reuse in different modules. How can I do that?

I know that I can define an analog function but this should be do into the module core and I cannot use this function outside the module where it was defined. Is it right?

I can use `define statement directive but I cannot use internal variables. I should define all variables (even those that are specific to the statement) in the module where directive is used.

Finally, I would like to find a solution to have a file with a set of functions which can have internal variables (just defined within the scope of the function) and could be called from different modules (like Matlab function for example). Possible or not?

Thank you in advance for your help,
Thomas.
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2384
Silicon Valley
Re: Functions outside module with internal variables
Reply #1 - Jul 30th, 2015, 7:40am
 
In Verilog, functions cannot hold state. So it is possible define a function with internal variables, but those variables are all unset as you enter the function (they do not remember their values from a previous call).

You cannot defind a function outside a module, but in general you should be able to define it in a particular module and call it from another using hierarchical references. The language itself supports this, but your simulator may not. The only other option would be to use defines.

-Ken
Back to top
 
 
View Profile WWW   IP Logged
PN03
New Member
*
Offline



Posts: 8
France
Re: Functions outside module with internal variables
Reply #2 - Aug 3rd, 2015, 1:04am
 
Hi Ken,

Thank you for your quick answer. So the only possibility to have local variables in my functions is to put them as analog functions in a specific module (named for example special_functions) with no inout port. Then I instantiate the module in other modules and I could call my analog functions ?

My simulator is Eldo so it takes into account the hierarchical reference.

Best regards,
Thomas.
Back to top
 
 
View Profile   IP Logged
PN03
New Member
*
Offline



Posts: 8
France
Re: Functions outside module with internal variables
Reply #3 - Aug 3rd, 2015, 1:15am
 
Another important question: analog functions seem to be limited to only one output variable (the variable implicitly declared by the name of the function). How can I have multiple output?

Many thanks,
Thomas.
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2384
Silicon Valley
Re: Functions outside module with internal variables
Reply #4 - Aug 3rd, 2015, 9:36am
 
You can place a direction on the function's arguments. By default they are inputs, but you can declare them to be outputs or inouts.

I did not understand your previous question. Please distinguish between local variables, which Verilog functions provide, and state variables, which Verilog functions do not provide. In other words, unlike normal module variables, variables (local variables) in functions are not state variable (they do not retain their value between calls).

-Ken
Back to top
 
 
View Profile WWW   IP Logged
PN03
New Member
*
Offline



Posts: 8
France
Re: Functions outside module with internal variables
Reply #5 - Aug 4th, 2015, 12:50am
 
Thank you Ken.

My question was about how to call a function of a module in another module? I didn't find how. Instantiate the module is ok, but use its own function in the module, it doesn't work...

I understood the difference between state variables and local variables. Maybe my sentence was confusing you.

Thomas.
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2384
Silicon Valley
Re: Functions outside module with internal variables
Reply #6 - Aug 4th, 2015, 3:36pm
 
To call a function defined in a different module, you need to use a hierarchical reference. I think you can construct it from the module name and the function name, if not, you would use an instance name and function name. For example, if the module that contains the function definition is named foo, and the function is named bar, then you would call it using foo.bar().

-Ken
Back to top
 
 
View Profile WWW   IP Logged
PN03
New Member
*
Offline



Posts: 8
France
Re: Functions outside module with internal variables
Reply #7 - Aug 5th, 2015, 12:27am
 
Thanks Ken. I've already try this construction but it doesn't work. I made two modules: "Specific_Functions" (with no inout) which contained my function "Func1" (one argument) and "Test_Function" in which I would call Func1.

In the Test_Function I instantiate the module Specific_Function with the line:

Specific_Functions spfunc();

Then I try to use the function with the command:

k = spfunc.Func1(m);

The verilog compiler gave the error:

[Error] Symbol spfunc.Func1(m) is not defined as a function

What I'm missing?

Thomas.
Back to top
 
 
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2384
Silicon Valley
Re: Functions outside module with internal variables
Reply #8 - Aug 6th, 2015, 5:27pm
 
You are missing examples that we can look at to see if you are doing this correctly.

-Ken
Back to top
 
 
View Profile WWW   IP Logged
PN03
New Member
*
Offline



Posts: 8
France
Re: Functions outside module with internal variables
Reply #9 - Aug 10th, 2015, 12:55am
 
Here is an example of what I'm doing. Ultimately, the special_function module should be place in a separate file.

Code:
`include "constants.vams"
`include "disciplines.vams"

module special_functions();

  analog function real maxValue;
    input n1,n2 ;
    real n1,n2 ;
    begin
	maxValue = (n1 > n2) ? n1 : n2 ;
    end
  endfunction

endmodule

module blackbox(in1,in2,out);

  inout in1,in2,out;
  electrical in1,in2,out;

  special_functions sp_func();

  real val1,val2;
  analog begin
    val1 = V(in1);
    val2 = V(in2);
    //V(out) <+ special_functions.maxValue(val1,val2);
    V(out) <+ sp_func.maxValue(val1,val2);
  end

endmodule 



In the attached file, you'll find the compilation error.

Thank you for your help,
Thomas.
Back to top
 

Screenshot_012.png
View Profile   IP Logged
Ken Kundert
Global Moderator
*****
Offline



Posts: 2384
Silicon Valley
Re: Functions outside module with internal variables
Reply #10 - Aug 10th, 2015, 4:16pm
 
It may be that your simulator does not support hierarchical references to analog functions.

What you did should work, but you might also try an alternative approach. I don't think it is necessary to actually instantiate the special_functions module. Instead you could just try calling special_functions.maxValue().

-Ken

Back to top
 
 
View Profile WWW   IP Logged
PN03
New Member
*
Offline



Posts: 8
France
Re: Functions outside module with internal variables
Reply #11 - Aug 11th, 2015, 12:49am
 
Hi Ken,

I've already try this by commenting the instantiation of the module and use the line V(out) <+ special_functions.maxValue(val1,val2); but it didn't work too. The compilation error is the same.

My compiler is Questa ADMS. If it doesn't support hierarchical reference for analog functions, I'll try to find another solution...  :'(

Thank you for your help Ken.

Best regards,
Thomas.
Back to top
 

Screenshot_013.png
View Profile   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1998
Massachusetts, USA
Re: Functions outside module with internal variables
Reply #12 - Aug 26th, 2015, 1:45pm
 
Hierarchical references of analog functions seems like a rat's nest of complications from the implementation side: if moduleA calls moduleB.functionB with a bias-dependent argument, then moduleA will need derivatives of functionB, which may not have been computed when moduleB was compiled.
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
Geoffrey_Coram
Senior Fellow
******
Offline



Posts: 1998
Massachusetts, USA
Re: Functions outside module with internal variables
Reply #13 - Aug 26th, 2015, 1:46pm
 
I'd suggest trying macros; note that you can declare variables inside of named blocks.  Would something like this work?

`define myfunc(result, arg1, arg2) \
 begin : myfunc_block1 \
   real var1; \
   var1 = sqrt(arg1); \
   result = var1*arg1 + arg2; \
 end \
Back to top
 
 

If at first you do succeed, STOP, raise your standards, and stop wasting your time.
View Profile WWW   IP Logged
PN03
New Member
*
Offline



Posts: 8
France
Re: Functions outside module with internal variables
Reply #14 - Aug 27th, 2015, 12:54am
 
Hi,

Thank you for these precisions. I had not considered to use named blocks in order to get local variables. That’s a good solution.

Actually I did it in another way. I defined in a Verilog-A file several analog functions (with local variables) and I used the `include command inside the module definition (in another file) to access to these functions.

File A.va

Code:
analog function real myfunc(param1,param2);
	input param1…
	…
endfunction 



File B.va

Code:
module foo(in,out);
	inout in,out;
	…
	…
	`include “File A.va”
	analog begin
		…
	end
endmodule 




Which is the best practice do you think?

Best regards,
Thomas.
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.