Hi all, I am designing a PLL at 1GHz with output tracking the input (no divider). I am using a PFD/CP with RC//C loop filter, and my VCO is a delay-line type ring oscillator. I chose a phase margin=60 degrees, damping factor zeta=1, the loop bandwidth=25MHz, and the natural frequency=10MHz.

When I went to Cadence transistor-level simulation, I could always see when the control voltage approaches the voltage required for locking (close to 0.7V in my case), it always has a low frequency ripple on it. I've attached the settling behavior of the control voltage. The ripple is about 20MHz and has a peak-peak amplitude of about 40mV.

I've tried to replace the VCO with an ideal VCO and the loop locked quietly with only high frequency ripple (frequency same as the reference) of about 1mV, so I assume the problem comes from my VCO. But my VCO works good individually as a block with a good linearity in the range of interest. I also tried to add two vcvs as buffers before and after the VCO in the PLL, but that didn't help.

I don't quite understand where the low frequency (20MHz) ripple comes from and how to solve the problem. I will appreciate if you can give any inputs or suggestions!

Faye

Hi Raj,

The reference frequency is 1GHz, Kvco is pretty high at about 1.6GHz*2pi/V since it is a ring oscillator. Icp is 50uA and R=1.5K, C1=20pF, C2=2pF. The bandwidth is about 25MHz based on the parameters.

Thanks,
Faye

Faye wrote on Jun 17^th, 2015, 8:28am:


Good grief.  
First, look at your architecture.  
Do you really want a DLL instead of a PLL?

If you *really* want a PLL with PD/CP/LF, then there are some well known ratios of Refclk to LF bandwidth, which I'm pretty sure are being violated here.

Last, think about your KVCO.  
You didn't spec your supply, but say it's 1V.  You don't want to operate near the rails.  You didn't spec your pull range, but say it's +/- 100 MHz.  So you'd want a little more than 200 MHz / V, about a factor of 5-10 less than you have now.  Excess gain will pick up noises.

Wave