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CML buffer Band width extension techniques (Read 7014 times)
Larry_80
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CML buffer Band width extension techniques
May 10th, 2015, 9:03pm
 
Hello Experts,
Please can anyone advice on the preferred bandwidth extension techniques commonly used for CML buffers in industry? I know we have passive inductive peaking, and source degeneration using resistor+cap. Please can anyone advice on what method is commonly used in industry considering its for low voltage application
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raja.cedt
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Re: CML buffer Band width extension techniques
Reply #1 - May 10th, 2015, 11:40pm
 
For broadband operation inductive peaking is the best option, it comes only area overhead. The problem RC degeneration is it will decrease dc gain and it can only improve the bandwidth if the input pole is dominate one.

Raj.
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Larry_80
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Re: CML buffer Band width extension techniques
Reply #2 - May 11th, 2015, 3:44am
 
Thanks Raj for your response. Can you expand on why you think RC degeneration only works if the input pole is dominant? As far as i know it doesn't matter if the dominant pole is from the input or output. Usually the dominant pole is the output pole, in which case you can still make the RC degeneration work. If you do the simple hand analysis, the degeneration produces an extra pole and a zero. If one makes the zero coincident with the dominant pole, then we are only limited by the pole created by the degeneration, hence we can control that to extend the bandwidth. Furthermore, while RC degeneration does reduce the small signal gain, it has the advantage of also reducing the input impedance (by virtue of degeneration), hence the preceding stage sees a smaller loading. Please i stand corrected and i am open to anyone clarifying all the points i made.
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raja.cedt
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Re: CML buffer Band width extension techniques
Reply #3 - May 11th, 2015, 6:23am
 
Hello..
With degeneration you will loss dc gain, so instead of using degeneration why cant you reduce the load resister which reduces gain and improves your bandwidth with out going for RC degeneration.
With degeneration input cap will decrease hence the pole created by preceding stage resistance and this cap will move based on your gm*rs.
Hope this helps, otherwise ask me I can explain in detail with some small signal model.

Thanks,
Raj.

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bharat
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Re: CML buffer Band width extension techniques
Reply #4 - Aug 1st, 2015, 8:32am
 
Raj,
For High Speed applications, the gain of CML buffer should be linear and gm in itself is non-linear ( parabolic) function of current. For input range of CML, the linearity can be achieved only by degeneration. Therefore throwing away DC gain is desired.
Also, attenuating DC gain is a type of Equalization ( De-emphasis).
These effects, one may not get by simply reducing the load resistance.

Thanks
-Bharat
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bharat
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Re: CML buffer Band width extension techniques
Reply #5 - Aug 1st, 2015, 8:50am
 
Larry_80 wrote on May 10th, 2015, 9:03pm:
Hello Experts,
Please can anyone advice on the preferred bandwidth extension techniques commonly used for CML buffers in industry? I know we have passive inductive peaking, and source degeneration using resistor+cap. Please can anyone advice on what method is commonly used in industry considering its for low voltage application


In addition to above mentioned techniques, followings are commonly used:

1. Negative impedance circuit, this helps in reducing the cap load of preceding stage ( at the cost of current) and in turn helps in improving BW ( gm/Cload), Cload is reducing.

2. This one is known as Cap Neutralization. You can refer Fig 5 of Razavi's paper
'10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18-
m CMOS Technology'.
In this fig M7 and M8 caps are helping in reducing the input caps of M1 & M2 and in turn increasing the BW.

You can write me back, if you want further small signal analysis.

Thanks
-Bharat


 
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