Hi,

I simulate the following code with SMASH.

Code:

`timescale 100ps / 1ps
`include "disciplines.vams"

module testbench ();
    electrical gnd;
    ground gnd;

    reg clk;
    initial clk=0;
    wire b;
    wire out1;

    always begin
	#10
	clk=1;
	#10
	clk=0;
	#10
	clk=1'bx;
	#10
	clk=0;
	#10
	clk=1'bz;
    end

    buffer buf0 (b, clk);
    resistor #(.r(100k)) r0 (b, gnd);
//    sinVarFreq svf0 (out1, gnd);
endmodule

module buffer (out, in);
    output out;
    input in;

    assign out = in;
endmodule 

I get the transient of the logic and resister current as in the picture:





The current through the resistor from 0 increasing to larger, although the voltage I think changes in the same way with time. How to understand the current curve?

Thanks,

Thank AMS expert. You exclude me one direction.
Yes, my next question is why the digital buffer does not drive the resistor? It needs a d2a module to adapter between them?

Hi,

After several trials with the example, I am still puzzled about the resistor in the module. I have tested input value to resistor. It is found that it only accepts logic '1' or '0'. The current does change when there is one '1' at one of the two pins, but wire b logic does not show impact on the current.


In the following code,


Code:

module testbench ();
    electrical gnd;
    ground gnd;

    reg clk;
    initial clk=0;
    wire b;
    wire out1;

    always begin
	#100
	clk=1;
	#100
	clk=0;
	#10
	clk=1'bx;
	#100
	clk=0;
	#10
	clk=1'bz;
    end

    buffer buf0 (b, clk);
    resistor #(.r(10)) r0 (b, 1);
endmodule   

The current image is as below:

http://i58.tinypic.com/2jdjgvt.png

I cannot figure out how the vertical axis values come out. Its maxim is Ampere?


When a number, such as '19' instead of '1' or '0' input, there is the following error message:

ERROR: instantiation of SPICE primitive 'resistor' failed (instance and model do not match: cannot connect a non-signal to the SPICE port 'SPICE Port', except "1'b1", "1'b0", "1" and "0"; actual expression has to be either a concatenation, or a part select or an bit select made of signals)

Although wire b has logic '1' and '0', it does not change the resistor current in the image.

Could you explain it to me?

Thanks,

No, I have never used Smash.

It is odd that you never plot the voltage, nor have you given any indication that you have provided a mapping from logic value to voltage levels.

-Ken