wang072711
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I generated the layout using encounter. Passed DRC and LVS in cadence virtuoso. Things went wrong when I extracted the layout and running post-simualtion.
Then I checked the extracted calibre view schematic. there are floating nets for some PMOS and NMOS.
I tried with different extraction type. when I using C+CC or NO R/C for PEX, there are no problem. Post-sims give the correct waveforms
But when I extracted with R. things went wrong.
I also tried a smaller design with only Four logic gates, and make sure that the routing is very short. Still the same problem
Also tried to exclude the parasitics from the power line. didn't work.
Any suggestion why or how to debug this?
thank you so much!!
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